In a large scale logic circuit design, redundant logic circuits, in other words, overlapping logic circuits, are integrated and shared on the basis of logic design information of a logic circuit. In this way, the logic circuit is reduced, and thus an amount of hardware is reduced.
For example, JP-A-10-021291 discloses a logic synthesis method and a logic synthesis device using similar partial circuit extraction. In JP-A-10-021291, it is proposed that a hardware description language is inputted, a common logic is extracted from inputted logic information, and the common logic is converted into a form to be shared and referred as a low-level layer while considering synthesis performance. A common logical formula is detected in order to share a calculating unit.
On the other hand, JP-A-11-85832 discloses a circuit conversion method, a circuit design support device, and a recording medium. In JP-A-11-85832, it is proposed that a correspondence relationship between a control condition and a data calculator is extracted from inputted circuit description, and the control condition and the data calculator are integrated together on the basis of the determination of the data calculator.
JP-A-9-34927 discloses a logic simulation device and a logic circuit information creating method. In JP-A-9-34927, it is proposed that a conditional statement indicating a condition of input versus output is searched from input macro logic description information, intermediate logic description information to which state transition information is added on the basis of the searched conditional statement is generated, a logic simulation of the input macro logic description information or the like is performed and state value information is outputted, a fixed conditional statement for redundant function is determined and extracted on the basis of the state value information, and a new logic description is generated by deleting the fixed conditional statement from the input macro logic description information on the basis of the determination result.
However, in case a redundant register or counter are purposely arranged by a designer of the logic circuit, the purposed redundant register and counter are recognized as a necessary function, and therefore, not shared based on the conventional logic design information. Consequently, according to the above described method in related art, a logic circuit including the purposed redundant register and counter is not detected as a common logic but still remains. This may cause problems in circuit size, power consumption, and verifiability of a large scale integrated circuit (LSI).